In-cell self capacitive touch control display panel and manufacture method thereof

ABSTRACT

The present invention provides an in-cell self capacitive touch control display panel and a manufacture method thereof. The in-cell self capacitive touch control display panel comprises: an array substrate, a CF substrate and a liquid crystal layer arranged between the array substrate and the CF substrate, and light is incident from a CF substrate side, and exits out of an array substrate side. The array substrate comprises: a plurality of gate scan lines ( 11 ) separately arranged along a horizontal direction, a plurality of data lines ( 41 ) separately arranged along a vertical direction, and a plurality of pixel electrodes ( 50 ) aligned in array; a touch scanning line is commonly shared with the gate scan line ( 11 ), and a touch receiving line is commonly shared with the data line ( 41 ), and a touch control self capacitance is commonly shared with the pixel electrode ( 50 ), under the premise of not adding more to the present process flow of the array substrate, the in-cell self capacitive touch control function can be realized and the driving cost of the panel can be reduced. The manufacture method of the in-cell self capacitive touch control display panel can reduce the driving cost of the panel without adding more to the present process flow of the array substrate.

FIELD OF THE INVENTION

The present invention relates to a display technology field, and moreparticularly to an in-cell self capacitive touch control display paneland a manufacture method thereof.

BACKGROUND OF THE INVENTION

With the rapid development of the display technology, the touch controldisplay panel has been widely applied and accepted, used by the people.For example, the smart phone, the flat panel computer and etc. all usethe touch control display panel. The touch control display panel is tocombine the touch control panel and the liquid display panel as one tomake the liquid crystal display panel equipped with functions of displayand sensing the touch control inputs at the same time.

Generally, the liquid crystal panel mainly comprises a Color Filter(CF), a Thin Film Transistor Array Substrate (TFT Array Substrate) and aLiquid Crystal Layer positioned inbetween. The working principle is thatthe light of backlight module is reflected to generate images byapplying driving voltages to the two glass substrate for controlling therotations of the liquid crystal molecules. According to the orientationof the liquid crystal, the liquid crystal display panels in themainstream market can be categorized into several types, which areVertical Alignment (VA), Twisted Nematic (TN) or Super Twisted Nematic(STN), In-Plane Switching (IPS) and Fringe Field Switching (FFS). In theIPS type liquid crystal display panel, the liquid crystal molecules areoriented to be parallel relative to the substrate surface, and byapplying the transverse electrical field for controlling the rotationsof the liquid crystal molecules.

The TFT array substrate is an important component of the liquid crystaldisplay panel. The TFT substrate generally comprises data lines, scanlines, common electrode lines, common electrodes, pixel electrodes andTFTs. Each pixel is electrically coupled to one TFT. The Gate of the TFTis coupled to a horizontal scan line, and Source of the TFT is coupledto a vertical data line, and the Drain is coupled to the pixelelectrode. The enough voltage is applied to the level scan line, and allthe TFTs electrically coupled to the scan line are activated. Thus, thesignal voltage on the data line can be written into the pixel to controlthe transmittances of different liquid crystals to achieve the displayeffect.

The touch control display panels can be categorized into four types ofresistive, capacitive, optics, surface acoustic wave according to thesensing technology. At present, the main stream touch control technologyis the capacitive type. The capacitive type can be further categorizedinto self capacitive type and mutual capacitive type. The touch displaypanel can be categorized according to different structures into: Oncell, In Cell and Out Cell. The In Cell touch display panel possessesmany advantages of being light and thin, frame free and achievable offull plane design, and becomes the research hot spot in the presenttouch control technology field.

The in-cell self capacitive touch control display panel according toprior art generally requires one set of touch control circuit (includingthe touch scanning line, the touch receiving line and the touch controlself capacitance) and the driving control part to realize the in-cellself capacitive touch control function. There is a certain difficultydegree for the manufacture processes of the panel and the driving costof the panel is higher.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide an in-cell selfcapacitive touch control display panel, of which under the premise ofnot adding more to the present process flow of the array substrate, thein-cell self capacitive touch control function can be realized and thedriving cost of the panel can be reduced.

Another objective of the present invention is to provide a manufacturemethod of the in-cell self capacitive touch control display panel canreduce the driving cost of the panel without adding more to the presentprocess flow of the array substrate.

For realizing the aforesaid objectives, the present invention providesan in-cell self capacitive touch control display panel, comprising: anarray substrate, a CF substrate and a liquid crystal layer arrangedbetween the array substrate and the CF substrate, and light is incidentfrom a CF substrate side, and exits out of an array substrate side;

the array substrate comprises: a plurality of gate scan lines separatelyarranged along a horizontal direction, a plurality of data linesseparately arranged along a vertical direction, and a plurality of pixelelectrodes aligned in array, and the plurality of gate scan linesseparately arranged along the horizontal direction and the plurality ofdata lines separately arranged along the vertical direction are mutuallyinsulated and staggered to divide a plurality of sub pixel areas; eachpixel electrode is correspondingly located in one sub pixel area;

a touch scanning line is commonly shared with the gate scan line, and atouch receiving line is commonly shared with the data line, and thetouch control self capacitance is commonly shared with the pixelelectrode;

time of one frame of image is divided into a display period and a touchcontrol period; in the display period, the gate scan line transmits agate scan signal, and the data line transmits a pixel gray scale signal,and the pixel electrode is employed to form a storage capacitor and aliquid crystal capacitor; in the touch control period, the gate scanline is employed to be the touch scanning line to transmit a touchscanning signal, and the data line is employed to be the touch receivingline to sense a touch signal, and the pixel electrode is employed to bethe touch control self capacitance.

The array substrate further comprises: a TFT located correspondingly toeach pixel electrode, and common electrodes located opposite to thepixel electrodes;

a gate isolation layer covering the gate scan line, a gate of the TFT,and the data line is located on the gate isolation layer, and an islandshape active layer of the TFT is located on the gate isolation layer,and a source and a drain of the TFT are respectively coupled to theisland shape active layer, and the pixel electrode is located on thegate isolation layer and coupled to a drain of the TFT, and aninsulation protective layer covering the data line, the pixel electrode,the source and the drain of the TFT, and the common electrode is pavedon the insulation protective layer.

The pixel electrode is flat, and the common electrode has a whole sheetstructure covering all the sub pixel areas; the common electrode isprovided with a plurality of long strip via holes in a regioncorresponding to each pixel electrode.

All materials of the gate scan line, the data line, and the gate, thesource, the drain of the TFT are one or more combination of molybdenum,aluminum and copper, and all thicknesses are 3000-6000 Å.

Both materials of the pixel electrode and the common electrode are ITO,and both thicknesses are 400-1000 Å.

Both materials of the gate isolation layer and the insulation protectivelayer are Silicon Nitride, and both thicknesses are 2000-5000 Å;material of the island shape active layer is amorphous silicon andn-type heavy doped amorphous silicon, and a thickness of the islandshape active layer is 1500-3000 Å.

The present invention further provides a manufacture method of anin-cell self capacitive touch control display panel, comprising stepsof:

step 1, providing a substrate and deposing a first metal layer on thesubstrate, and implementing pattern process to the first metal layer toform a gate scan line and a gate in one with the gate scan line;

the gate scan line is also employed to be a touch scanning line;

step 2, deposing a gate isolation layer on the gate scan line and thegate, and deposing a semiconductor layer on the gate isolation layer,then implementing pattern process to the semiconductor layer to form anisland shape active layer;

step 3, deposing a second metal layer on the island shape active layerand the gate isolation layer, then implementing pattern process to thesecond metal layer to form a data line, a source in one with the dataline and connected with the island shape active layer, and a drainconnected to the island shape active layer;

the gate, the source, the drain and the island shape active layerconstruct a TFT;

the data line is also employed to be a touch receiving line;

step 4, deposing a first transparent conductive thin film on the gateisolation layer, the data line, the source and the drain, thenimplementing pattern process to the first transparent conductive thinfilm to form a plurality of pixel electrodes aligned in array, and eachpixel electrode is correspondingly coupled to the drain of one TFT;

the pixel electrode is also employed to be a touch control selfcapacitance;

step 5, deposing an insulation protective layer on the data line, thepixel electrode, the source and the drain, and implementing patternprocess to the insulation protective layer;

step 6, deposing a second transparent conductive thin film on theinsulation protective layer, and implementing pattern process to thesecond transparent conductive thin film to form a whole sheet commonelectrode located opposite to all the pixel electrodes, and the wholesheet common electrode is provided with a plurality of long strip viaholes in a region corresponding to each pixel electrode.

manufacture of the array substrate is accomplished;

step 7, providing a CF substrate, and oppositely assembling the CFsubstrate and the array substrate, and injecting liquid crystals to forma liquid crystal layer.

In the step 1, the first metal layer is deposed by physical vapordeposition, and the pattern process to the first metal layer comprisesphotoresist coating, and implementing exposure, development, wet etchingand photoresist stripping with a mask;

in the step 2, the gate isolation layer and the semiconductor layer aredeposed by plasma enhanced chemical vapor deposition, and the patternprocess to the semiconductor layer comprises photoresist coating, andimplementing exposure, development, dry etching and photoresiststripping with a mask;

in the step 3, the second metal layer is deposed by physical vapordeposition, and the pattern process to the second metal layer comprisesexposure, development, wet etching and photoresist stripping;

in the step 4, the first transparent conductive thin film is deposed byphysical vapor deposition, and the pattern process to the firsttransparent conductive thin film comprises exposure, development, wetetching and photoresist stripping;

in the step 5, the insulation protective layer is deposed by plasmaenhanced chemical vapor deposition, and the pattern process to theinsulation protective layer comprises photoresist coating, andimplementing exposure, development, dry etching and photoresiststripping with a mask;

in the step 6, the second transparent conductive thin film is deposed byphysical vapor deposition, and the pattern process to the secondtransparent conductive thin film comprises photoresist coating, andimplementing exposure, development, wet etching and photoresiststripping.

Material of the first metal in the step 1, material of the second metallayer in the step 3 are one or more combination of molybdenum, aluminumand copper, and thicknesses are 3000-6000 Å.

Material of the gate isolation layer in the step 2, material of theinsulation protective layer in the step 5 are Silicon Nitride, andthicknesses are 2000-5000 Å; material of the semiconductor layer in thestep 2 is amorphous silicon and n-type heavy doped amorphous silicon,and a thickness of the island shape active layer is 1500-3000 Å;

material of the first transparent conductive thin film in the step 4,material of the second transparent conductive thin film in the step 6are ITO, and thicknesses are 400-1000 Å.

The present invention further provides a manufacture method of anin-cell self capacitive touch control display panel, comprising stepsof:

step 1, providing a substrate and deposing a first metal layer on thesubstrate, and implementing pattern process to the first metal layer toform a gate scan line and a gate in one with the gate scan line;

the gate scan line is also employed to be a touch scanning line;

step 2, deposing a gate isolation layer on the gate scan line and thegate, and deposing a semiconductor layer on the gate isolation layer,then implementing pattern process to the semiconductor layer to form anisland shape active layer;

step 3, deposing a second metal layer on the island shape active layerand the gate isolation layer, then implementing pattern process to thesecond metal layer to form a data line, and a source in one with thedata line and connected with the island shape active layer, a drainconnected to the island shape active layer;

the gate, the source, the drain and the island shape active layerconstruct a TFT;

the data line is also employed to be a touch receiving line;

step 4, deposing a first transparent conductive thin film on the gateisolation layer, the data line, the source and the drain, thenimplementing pattern process to the first transparent conductive thinfilm to form a plurality of pixel electrodes aligned in array, and eachpixel electrode is correspondingly coupled to the drain of one TFT;

the pixel electrode is also employed to be a touch control selfcapacitance;

step 5, deposing an insulation protective layer on the data line, thepixel electrode, the source and the drain, and implementing patternprocess to the insulation protective layer;

step 6, deposing a second transparent conductive thin film on theinsulation protective layer, and implementing pattern process to thesecond transparent conductive thin film to form a whole sheet commonelectrode located opposite to all the pixel electrodes, and the wholesheet common electrode is provided with a plurality of long strip viaholes in a region corresponding to each pixel electrode.

manufacture of the array substrate is accomplished;

step 7, providing a CF substrate, and oppositely assembling the CFsubstrate and the array substrate, and injecting liquid crystals to forma liquid crystal layer;

wherein in the step 1, the first metal layer is deposed by physicalvapor deposition, and the pattern process to the first metal layercomprises photoresist coating, and implementing exposure, development,wet etching and photoresist stripping with a mask;

in the step 2, the gate isolation layer and the semiconductor layer aredeposed by plasma enhanced chemical vapor deposition, and the patternprocess to the semiconductor layer comprises photoresist coating, andimplementing exposure, development, dry etching and photoresiststripping with a mask;

in the step 3, the second metal layer is deposed by physical vapordeposition, and the pattern process to the second metal layer comprisesexposure, development, wet etching and photoresist stripping;

in the step 4, the first transparent conductive thin film is deposed byphysical vapor deposition, and the pattern process to the firsttransparent conductive thin film comprises exposure, development, wetetching and photoresist stripping;

in the step 5, the insulation protective layer is deposed by plasmaenhanced chemical vapor deposition, and the pattern process to theinsulation protective layer comprises photoresist coating, andimplementing exposure, development, dry etching and photoresiststripping with a mask;

in the step 6, the second transparent conductive thin film is deposed byphysical vapor deposition, and the pattern process to the secondtransparent conductive thin film comprises photoresist coating, andimplementing exposure, development, wet etching and photoresiststripping;

wherein material of the first metal in the step 1, material of thesecond metal layer in the step 3 are one or more combination ofmolybdenum, aluminum and copper, and thicknesses are 3000-6000 Å;

wherein material of the gate isolation layer in the step 2, material ofthe insulation protective layer in the step 5 are Silicon Nitride, andthicknesses are 2000-5000 Å; material of the semiconductor layer in thestep 2 is amorphous silicon and n-type heavy doped amorphous silicon,and a thickness is 1500-3000 Å;

material of the first transparent conductive thin film in the step 4,material of the second transparent conductive thin film in the step 6are ITO, and thicknesses are 400-1000 Å.

The benefits of the present invention are: in the in-cell selfcapacitive touch control display panel and the manufacture methodthereof provided by the present invention, a touch scanning line iscommonly shared with the gate scan line, and a touch receiving line iscommonly shared with the data line, and a touch control self capacitanceis commonly shared with the pixel electrode, under the premise of notadding more to the present process flow of the array substrate, thein-cell self capacitive touch control function can be realized and thedriving cost of the panel can be reduced.

In order to better understand the characteristics and technical aspectof the invention, please refer to the following detailed description ofthe present invention is concerned with the diagrams, however, providereference to the accompanying drawings and description only and is notintended to be limiting of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The technical solution and the beneficial effects of the presentinvention are best understood from the following detailed descriptionwith reference to the accompanying figures and embodiments.

In drawings,

FIG. 1 is a top view diagram of an array substrate of an in-cell selfcapacitive touch control display panel according to the presentinvention;

FIG. 2 is a driving sequence diagram of an in-cell self capacitive touchcontrol display panel according to the present invention;

FIG. 3 is a touch control driving principle diagram of an in-cell selfcapacitive touch control display panel according to the presentinvention;

FIG. 4 is a flowchart of a manufacture method of an in-cell selfcapacitive touch control display panel according to the presentinvention;

FIG. 5 is a diagram of the step 1 in the manufacture method of thein-cell self capacitive touch control display panel according to thepresent invention;

FIG. 6 is a diagram of the step 2 in the manufacture method of thein-cell self capacitive touch control display panel according to thepresent invention;

FIG. 7 is a diagram of the step 3 in the manufacture method of thein-cell self capacitive touch control display panel according to thepresent invention;

FIG. 8 is a diagram of the step 4 in the manufacture method of thein-cell self capacitive touch control display panel according to thepresent invention;

FIG. 9 is a diagram of the step 6 in the manufacture method of thein-cell self capacitive touch control display panel according to thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

For better explaining the technical solution and the effect of thepresent invention, the present invention will be further described indetail with the accompanying drawings and the specific embodiments.

The present invention first provides an in-cell self capacitive touchcontrol display panel, comprising: an array substrate, a CF substrateand a liquid crystal layer arranged between the array substrate and theCF substrate, and light is incident from a CF substrate side, and exitsout of an array substrate side.

Please refer to FIG. 1. The array substrate comprises:

a plurality of gate scan lines 11 separately arranged along a horizontaldirection;

a plurality of data lines 41 separately arranged along a verticaldirection, and the plurality of gate scan lines 11 separately arrangedalong the horizontal direction and the plurality of data lines 41separately arranged along the vertical direction are mutually insulatedand staggered to divide a plurality of sub pixel areas;

a plurality of pixel electrodes 50 aligned in array, and each pixelelectrode 50 is correspondingly located in one sub pixel area, and thepixel electrode 50 is flat;

a TFT T correspondingly located to each pixel electrode 50;

and a whole sheet common electrode 60 located opposite to all the pixelelectrodes 50, and the whole sheet common electrode 60 is provided witha plurality of long strip via holes 61 in a region corresponding to eachpixel electrode 50 for forming a transverse electrical field between thepixel electrodes 50 and the whole sheet common electrode 60.

A gate isolation layer (not shown) covers the gate scan line 11, a gate13 of the TFT T; the data line 41 is located on the gate isolationlayer; an island shape active layer 30 of the TFT is located on the gateisolation layer; a source 45 and a drain 47 of the TFT T arerespectively coupled to the island shape active layer 30; the pixelelectrode 50 is located on the gate isolation layer and coupled to adrain 47 of the TFT T. An insulation protective layer (not shown) coversthe data line 41, the pixel electrode 51, the source 45 and the drain 47of the TFT T; the whole sheet common electrode 60 is paved on theinsulation protective layer.

Specifically, all materials of the gate scan line 11, the data line 41,and the gate 13, the source 45, the drain 47 of the TFT T are one ormore combination of molybdenum (Mo), aluminum (Al) and copper (Cu), andall thicknesses are 3000-6000 Å; both materials of the pixel electrode50 and the common electrode 60 are Indium Tin Oxide (ITO), and boththicknesses are 400-1000 Å; both materials of the gate isolation layerand the insulation protective layer are Silicon Nitride (SiNx), and boththicknesses are 2000-5000 Å; material of the island shape active layer30 is amorphous silicon and n-type heavy doped amorphous silicon, and athickness of the island shape active layer is 1500-3000 Å.

Particularly, a touch scanning line is commonly shared with the gatescan line 11, and a touch receiving line is commonly shared with thedata line 41, and a touch control self capacitance is commonly sharedwith the pixel electrode 50. Under the premise of not adding more to thepresent process flow of the array substrate, the in-cell self capacitivetouch control function can be realized.

Please refer to FIG. 2 and FIG. 3 at the same time. The in-cell selfcapacitive touch control display panel of the present invention performsdisplay and touch control in time division. That is to say that time ofone frame of image is divided into a display period and a touch controlperiod; in the display period, the gate scan line 11 transmits a gatescan signal, and the data line 41 transmits a pixel gray scale signal,and the pixel electrode 50 is employed to form a storage capacitor and aliquid crystal capacitor for normally display images; in the touchcontrol period, the gate scan line 11 is employed to be the touchscanning line to transmit a touch scanning signal, and the data line 41is employed to be the touch receiving line to sense a touch signal, andthe pixel electrode 50 is employed to be the touch control selfcapacitance for realizing the in-cell self capacitive touch controlfunction.

Specifically, as shown in FIG. 3, in the touch control period, supposingthat the nth gate scan line 11 transmits a touch scanning signal G(n),and all TFTs in the nth row is on, the respective pixel electrodes 50 inthe nth row are respectively conducted with one corresponding data line41 through one TFT, and pulse signals are respectively transmitted withrespective data lines 41. At this moment, if the finger touches thepixel electrode 50 at the nth row and mth column (m is an positiveinteger), the capacitance at the pixel electrode 50 will be affected,and meanwhile, the pulse signal D(m) transmitted in the mth data line 41conducted with the pixel electrode 50 changes with sensing thedifference of the capacitance. In other words, the mth data line 41 isemployed to be the touch receiving signal to sense a touch signal.Accordingly, the position where the touch signal is can be determined.

Both the gate scan signal and the touch scanning signal are provided bythe gate driver. There is no need to add the additional driving controlpart for realizing the touch control function, and the driving cost ofthe panel can be reduced.

The structure of the CF substrate is the same as the CF substrate in theIPS type liquid crystal display panel according to prior art, andcomprises components of color film photoresist, a black matrix,photospacers and alignment films. The detail description is omittedhere.

Please refer to FIG. 4. The present invention further provides amanufacture method of an in-cell self capacitive touch control displaypanel, comprising steps of:

step 1, as shown in FIG. 5, providing a substrate and deposing a firstmetal layer on the substrate, and implementing pattern process to thefirst metal layer to form a gate scan line 11 and a gate 13 in one withthe gate scan line 13; the gate scan line 11 is also employed to be atouch scanning line.

Specifically, in the step 1, the first metal layer is deposed byphysical vapor deposition (PVD), and the pattern process to the firstmetal layer comprises photoresist coating, and implementing exposure,development, wet etching and photoresist stripping with a mask.

Material of the first metal layer is one or more combination of Mo, Aland Cu, and a thickness is 3000-6000 Å.

step 2, as shown in FIG. 6, deposing a gate isolation layer on the gatescan line 11 and the gate 13, and deposing a semiconductor layer on thegate isolation layer, then implementing pattern process to thesemiconductor layer to form an island shape active layer 30.

Specifically, in the step 2, the gate isolation layer (not shown) andthe semiconductor layer are deposed by plasma enhanced chemical vapordeposition (PECVD), and the pattern process to the semiconductor layercomprises photoresist coating, and implementing exposure, development,dry etching and photoresist stripping with a mask.

Material of the gate isolation layer is SiNx, and a thickness is2000-5000 Å; material of the semiconductor layer is amorphous siliconand n-type heavy doped amorphous silicon, and a thickness is 1500-3000Å.

step 3, as shown in FIG. 7, deposing a second metal layer on the islandshape active layer 30 and the gate isolation layer, then implementingpattern process to the second metal layer to form a data line 41, and asource 45 in one with the data line 41 and connected with the islandshape active layer 30, a drain 47 connected to the island shape activelayer 30. The gate 13, the source 45, the drain 47 and the island shapeactive layer 30 construct a TFT T. The data line 41 is also employed tobe a touch receiving line.

Specifically, in the step 3, the second metal layer is deposed by PVD,and the pattern process to the second metal layer comprises exposure,development, wet etching and photoresist stripping.

Material of the second metal layer is one or more combination of Mo, Aland Cu, and a thickness is 3000-6000 Å.

step 4, as shown in FIG. 8, deposing a first transparent conductive thinfilm on the gate isolation layer, the data line 41, the source 45 andthe drain 47, then implementing pattern process to the first transparentconductive thin film to form a plurality of pixel electrodes 50 alignedin array, and each pixel electrode 50 is correspondingly coupled to thedrain 47 of one TFT T. The pixel electrode 50 is flat and also employedto be a touch control self capacitance.

Specifically, in the step 4, the first transparent conductive thin filmis deposed by PVD, and the pattern process to the first transparentconductive thin film comprises exposure, development, wet etching andphotoresist stripping.

Material of the first transparent conductive thin film is ITO, and athickness is 400-1000 Å.

step 5, deposing an insulation protective layer (not shown) on the dataline 41, the pixel electrode 50, the source 45 and the drain 47, andimplementing pattern process to the insulation protective layer to formcircular via holes in the peripheral wiring layout area and the Padarea.

Specifically, in the step 5, the insulation protective layer is deposedby PECVD, and the pattern process to the insulation protective layercomprises photoresist coating, and implementing exposure, development,dry etching and photoresist stripping with a mask.

Material of the insulation protective layer is SiNx, and a thickness is2000-5000 Å.

step 6, as shown in FIG. 9, deposing a second transparent conductivethin film on the insulation protective layer, and implementing patternprocess to the second transparent conductive thin film to form a wholesheet common electrode 60 located opposite to all the pixel electrodes50, and the whole sheet common electrode 60 is provided with a pluralityof long strip via holes 61 in a region corresponding to each pixelelectrode 50; manufacture of the array substrate is accomplished.

Specifically, in the step 6, the second transparent conductive thin filmis deposed by PVD, and the pattern process to the second transparentconductive thin film comprises photoresist coating, and implementingexposure, development, wet etching and photoresist stripping.

Material of the second transparent conductive thin film is ITO, and athickness is 400-1000 Å.

step 7, providing a CF substrate, and oppositely assembling the CFsubstrate and the array substrate, and injecting liquid crystals to forma liquid crystal layer.

The aforesaid method of the in-cell self capacitive touch controldisplay panel does not add more to the process flow. The manufacturedin-cell self capacitive touch control display panel performs display andtouch control in time division. That is to say that time of one frame ofimage is divided into a display period and a touch control period; inthe display period, the gate scan line 11 transmits a gate scan signal,and the data line 41 transmits a pixel gray scale signal, and the pixelelectrode 50 is employed to form a storage capacitor and a liquidcrystal capacitor for normally display images; in the touch controlperiod, the gate scan line 11 is employed to be the touch scanning lineto transmit a touch scanning signal, and the data line 41 is employed tobe the touch receiving line to sense a touch signal, and the pixelelectrode 50 is employed to be the touch control self capacitance forrealizing the in-cell self capacitive touch control function. Both thegate scan signal and the touch scanning signal are provided by the gatedriver. There is no need to add the additional driving control part forrealizing the touch control function, and the driving cost of the panelcan be reduced.

In conclusion, in the in-cell self capacitive touch control displaypanel and the manufacture method thereof according to the presentinvention, a touch scanning line is commonly shared with the gate scanline, and a touch receiving line is commonly shared with the data line,and a touch control self capacitance is commonly shared with the pixelelectrode, under the premise of not adding more to the present processflow of the array substrate, the in-cell self capacitive touch controlfunction can be realized and the driving cost of the panel can bereduced.

Above are only specific embodiments of the present invention, the scopeof the present invention is not limited to this, and to any persons whoare skilled in the art, change or replacement which is easily derivedshould be covered by the protected scope of the invention. Thus, theprotected scope of the invention should go by the subject claims.

What is claimed is:
 1. An in-cell self capacitive touch control displaypanel, comprising: an array substrate, a CF substrate and a liquidcrystal layer arranged between the array substrate and the CF substrate,and light is incident from a CF substrate side, and exits out of anarray substrate side; the array substrate comprises: a plurality of gatescan lines separately arranged along a horizontal direction, a pluralityof data lines separately arranged along a vertical direction, and aplurality of pixel electrodes aligned in array, and the plurality ofgate scan lines separately arranged along the horizontal direction andthe plurality of data lines separately arranged along the verticaldirection are mutually insulated and staggered to divide a plurality ofsub pixel areas; each pixel electrode is correspondingly located in onesub pixel area; a touch scanning line is commonly shared with the gatescan line, and a touch receiving line is commonly shared with the dataline, and a touch control self capacitance is commonly shared with thepixel electrode; time of one frame of image is divided into a displayperiod and a touch control period; in the display period, the gate scanline transmits a gate scan signal, and the data line transmits a pixelgray scale signal, and the pixel electrode is employed to form a storagecapacitor and a liquid crystal capacitor; in the touch control period,the gate scan line is employed to be the touch scanning line to transmita touch scanning signal, and the data line is employed to be the touchreceiving line to sense a touch signal, and the pixel electrode isemployed to be the touch control self capacitance.
 2. The in-cell selfcapacitive touch control display panel according to claim 1, wherein thearray substrate further comprises: a TFT located correspondingly to eachpixel electrode, and a plurality of common electrodes located oppositeto the pixel electrodes; a gate isolation layer covering the gate scanline, a gate of the TFT, and the data line is located on the gateisolation layer, and an island shape active layer of the TFT is locatedon the gate isolation layer, and a source and a drain of the TFT arerespectively coupled to the island shape active layer, and the pixelelectrode is located on the gate isolation layer and coupled to a drainof the TFT, and an insulation protective layer covering the data line,the pixel electrode, the source and the drain of the TFT, and the commonelectrode is paved on the insulation protective layer.
 3. The in-cellself capacitive touch control display panel according to claim 2,wherein the pixel electrode is flat, and the common electrode has awhole sheet structure covering all the sub pixel areas; the commonelectrode is provided with a plurality of long strip via holes in aregion corresponding to each pixel electrode.
 4. The in-cell selfcapacitive touch control display panel according to claim 2, wherein allmaterials of the gate scan line, the data line, and the gate, thesource, the drain of the TFT are one or more combination of molybdenum,aluminum and copper, and all thicknesses are 3000-6000 Å.
 5. The in-cellself capacitive touch control display panel according to claim 2,wherein both materials of the pixel electrode and the common electrodeare ITO, and both thicknesses are 400-1000 Å.
 6. The in-cell selfcapacitive touch control display panel according to claim 2, whereinboth materials of the gate isolation layer and the insulation protectivelayer are Silicon Nitride, and both thicknesses are 2000-5000 Å;material of the island shape active layer is amorphous silicon andn-type heavy doped amorphous silicon, and a thickness of the islandshape active layer is 1500-3000 Å.
 7. A manufacture method of an in-cellself capacitive touch control display panel, comprising steps of: step1, providing a substrate and deposing a first metal layer on thesubstrate, and implementing pattern process to the first metal layer toform a gate scan line and a gate in one with the gate scan line; thegate scan line is also employed to be a touch scanning line; step 2,deposing a gate isolation layer on the gate scan line and the gate, thendeposing a semiconductor layer on the gate isolation layer, andimplementing pattern process to the semiconductor layer to form anisland shape active layer; step 3, deposing a second metal layer on theisland shape active layer and the gate isolation layer, thenimplementing pattern process to the second metal layer to form a dataline, a source in one with the data line and connected with the islandshape active layer, and a drain connected to the island shape activelayer; the gate, the source, the drain and the island shape active layerconstruct a TFT; the data line is also employed to be a touch receivingline; step 4, deposing a first transparent conductive thin film on thegate isolation layer, the data line, the source and the drain, thenimplementing pattern process to the first transparent conductive thinfilm to form a plurality of pixel electrodes aligned in array, and eachpixel electrode is correspondingly coupled to the drain of one TFT; thepixel electrode is also employed to be a touch control self capacitance;step 5, deposing an insulation protective layer on the data line, thepixel electrode, the source and the drain, and implementing patternprocess to the insulation protective layer; step 6, deposing a secondtransparent conductive thin film on the insulation protective layer, andimplementing pattern process to the second transparent conductive thinfilm to form a whole sheet common electrode located opposite to all thepixel electrodes, and the whole sheet common electrode is provided witha plurality of long strip via holes in a region corresponding to eachpixel electrode. manufacture of the array substrate is accomplished;step 7, providing a CF substrate, and oppositely assembling the CFsubstrate and the array substrate, and injecting liquid crystals to forma liquid crystal layer.
 8. The manufacture method of the in-cell selfcapacitive touch control display panel according to claim 7, wherein inthe step 1, the first metal layer is deposed by physical vapordeposition, and the pattern process to the first metal layer comprisesphotoresist coating, and implementing exposure, development, wet etchingand photoresist stripping with a mask; in the step 2, the gate isolationlayer and the semiconductor layer are deposed by plasma enhancedchemical vapor deposition, and the pattern process to the semiconductorlayer comprises photoresist coating, and implementing exposure,development, dry etching and photoresist stripping with a mask; in thestep 3, the second metal layer is deposed by physical vapor deposition,and the pattern process to the second metal layer comprises exposure,development, wet etching and photoresist stripping; in the step 4, thefirst transparent conductive thin film is deposed by physical vapordeposition, and the pattern process to the first transparent conductivethin film comprises exposure, development, wet etching and photoresiststripping; in the step 5, the insulation protective layer is deposed byplasma enhanced chemical vapor deposition, and the pattern process tothe insulation protective layer comprises photoresist coating, andimplementing exposure, development, dry etching and photoresiststripping with a mask; in the step 6, the second transparent conductivethin film is deposed by physical vapor deposition, and the patternprocess to the second transparent conductive thin film comprisesphotoresist coating, and implementing exposure, development, wet etchingand photoresist stripping.
 9. The manufacture method of the in-cell selfcapacitive touch control display panel according to claim 7, whereinmaterial of the first metal in the step 1, material of the second metallayer in the step 3 are one or more combination of molybdenum, aluminumand copper, and thicknesses are 3000-6000 Å.
 10. The manufacture methodof the in-cell self capacitive touch control display panel according toclaim 7, wherein material of the gate isolation layer in the step 2,material of the insulation protective layer in the step 5 are SiliconNitride, and thicknesses are 2000-5000 Å; material of the semiconductorlayer in the step 2 is amorphous silicon and n-type heavy dopedamorphous silicon, and a thickness of the island shape active layer is1500-3000 Å; material of the first transparent conductive thin film inthe step 4, material of the second transparent conductive thin film inthe step 6 are ITO, and thicknesses are 400-1000 Å.
 11. A manufacturemethod of an in-cell self capacitive touch control display panel,comprising steps of: step 1, providing a substrate and deposing a firstmetal layer on the substrate, and implementing pattern process to thefirst metal layer to form a gate scan line and a gate in one with thegate scan line; the gate scan line is also employed to be a touchscanning line; step 2, deposing a gate isolation layer on the gate scanline and the gate, then deposing a semiconductor layer on the gateisolation layer, and implementing pattern process to the semiconductorlayer to form an island shape active layer; step 3, deposing a secondmetal layer on the island shape active layer and the gate isolationlayer, then implementing pattern process to the second metal layer toform a data line, a source in one with the data line and connected withthe island shape active layer, and a drain connected to the island shapeactive layer; the gate, the source, the drain and the island shapeactive layer construct a TFT; the data line is also employed to be atouch receiving line; step 4, deposing a first transparent conductivethin film on the gate isolation layer, the data line, the source and thedrain, then implementing pattern process to the first transparentconductive thin film to form a plurality of pixel electrodes aligned inarray, and each pixel electrode is correspondingly coupled to the drainof one TFT; the pixel electrode is also employed to be a touch controlself capacitance; step 5, deposing an insulation protective layer on thedata line, the pixel electrode, the source and the drain, andimplementing pattern process to the insulation protective layer; step 6,deposing a second transparent conductive thin film on the insulationprotective layer, and implementing pattern process to the secondtransparent conductive thin film to form a whole sheet common electrodelocated opposite to all the pixel electrodes, and the whole sheet commonelectrode is provided with a plurality of long strip via holes in aregion corresponding to each pixel electrode. manufacture of the arraysubstrate is accomplished; step 7, providing a CF substrate, andoppositely assembling the CF substrate and the array substrate, andinjecting liquid crystals to form a liquid crystal layer; wherein in thestep 1, the first metal layer is deposed by physical vapor deposition,and the pattern process to the first metal layer comprises photoresistcoating, and implementing exposure, development, wet etching andphotoresist stripping with a mask; in the step 2, the gate isolationlayer and the semiconductor layer are deposed by plasma enhancedchemical vapor deposition, and the pattern process to the semiconductorlayer comprises photoresist coating, and implementing exposure,development, dry etching and photoresist stripping with a mask; in thestep 3, the second metal layer is deposed by physical vapor deposition,and the pattern process to the second metal layer comprises exposure,development, wet etching and photoresist stripping; in the step 4, thefirst transparent conductive thin film is deposed by physical vapordeposition, and the pattern process to the first transparent conductivethin film comprises exposure, development, wet etching and photoresiststripping; in the step 5, the insulation protective layer is deposed byplasma enhanced chemical vapor deposition, and the pattern process tothe insulation protective layer comprises photoresist coating, andimplementing exposure, development, dry etching and photoresiststripping with a mask; in the step 6, the second transparent conductivethin film is deposed by physical vapor deposition, and the patternprocess to the second transparent conductive thin film comprisesphotoresist coating, and implementing exposure, development, wet etchingand photoresist stripping; wherein material of the first metal in thestep 1, material of the second metal layer in the step 3 are one or morecombination of molybdenum, aluminum and copper, and thicknesses are3000-6000 Å; wherein material of the gate isolation layer in the step 2,material of the insulation protective layer in the step 5 are SiliconNitride, and thicknesses are 2000-5000 Å; material of the semiconductorlayer in the step 2 is amorphous silicon and n-type heavy dopedamorphous silicon, and a thickness is 1500-3000 Å; material of the firsttransparent conductive thin film in the step 4, material of the secondtransparent conductive thin film in the step 6 are ITO, and thicknessesare 400-1000 Å.